Semiconductor memory array circuits are well known in the art. There are three types of memory cells which can electrically write data signals into a memory cell and electrically read data signals out of a selected memory cell.
The first type, using a capacitor, is called a Dynamic Random Access Memory (DRAM). The second type, using a latch, is called a Static Random Access Memory (SRAM). A third type using a floating gate to store charges, which controls the action of a channel of a transistor is called Electrically Erasable Programmable Read Only Memory (EEPROM).
In all three types of semiconductor memory array circuit, the memory cells are arranged in a matrix of columns and rows. A column line and a row line can select a particular select transistor which is connected to an associated memory cell. During writing, a data signal (which can be "1" or "0") to be stored in a selected memory cell is supplied on a column line. The activation of a particular row line, which is connected to the gate of a select transistor, causes the data signal to be passed through the select transistor associated with the select memory cell and to be stored in the select memory cell.
In a DRAM device the memory cell is a capacitor with one electrode of the capacitor connected to the selected transistor, and the other electrode of the capacitor connected to ground. The memory array is typically segmented into two sections. During read, the corresponding column lines of the two memory sections are pre-charged. The select capacitor in one memory section is connected to one pre-charged column line. A sense amplifier differentially senses the charges between the two pre-charged column lines.
In an SRAM device there are two column lines with two select transistors, causing the data signal and its complement to be stored in the latch. During read operation, a particular pair of column line is precharged. A particular row line is then activated turning on the pair of select transistors causing the state of the selected memory cell to be read out and supplied to the precharged column lines. The change on the charge of the pre-charged column lines from one another determines the state of the selected memory cell.
In U.S. Pat. No. 3,986,173 reference is made to the use of diodes to transfer data signals into a bipolar latch. However, the diodes were deemed not suitable and disclosure is made to the use of select transistors. In addition, that reference taught the use of tow column lines per latch. see also "Pinch Load resistors Shrink Bipolar Memory Cells" by S. K. Wiedmann, Electronics, Mar. 7, 1974, p. 130-133.
In a flash EEPROM, the charges stored on a floating gate of the selected transistor determines the amount of current that passes through the channel of the select transistor.
Semiconductor memory designers have sought to increase the density of semiconductor memory array circuit, by packing more memory cells in each integrated circuit. This has been accomplished primarily by reducing the size of the transistors which are used in the memory array circuit. However, each transistor is fabricated laterally or planarly on a semiconductor substrate, such as single crystalline silicon. Thus, select transistors take up lateral surface area on a semiconductor substrate.
Control circuits interfacing a row decoder and row lines for controlling the voltages applied to the row lines during read, erase, and program in an EEPROM device is also well known in the art. See for example, U.S. Pat. No. 4,427,918.